1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a self-extinguish type semiconductor device such as a gate turn-off thyristor, static induction thyristor and static induction transistor. The present invention also relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
The above mentioned self-extinguish type semiconductor device such as gate turn-off thyristor (GTO thyristor) and static induction thyristor (SI thyristor) have been widely used as a power semiconductor device and have been described in the following publications:
1. Junichi Nishizawa, "High Power Vertical Type Junction FET having Triode Characteristics", Nikkei Electronics, Sep. 27, 1971, pp. 50-61
2. J. Nishizawa, T. Terasaki and J. Sibata, "Field-Effect Transistor versus Analog Transistor (Static Induction Transistor)", IEEE Trans. on Electron Device, ED-22(4), 185, 1975
3. J. Nishizawa and K. Nakamura, Physiquee Appliquee, T13, 725, 1978
4. J. Nishizawa and Y, Otsubo, Tech. Dig. 1980 IEDM, 658, 1980
5. J. Nishizawa, T. Ohmi, T. Sha and K. Mototani, Technical Report of Electron and Communication Society, ED81-84, 1981
6. M. Ishidoh, et al, "Advanced High Frequency GTO", Proc, ISPSD, 189, 1988
7. B. J. Baliga, et al, "The Evolution of Power Device Technology", IEEE Trans. on Electron Device, ED-31, 1570, 1984
8. M. Amato, et al, "Comparison of Lateral and Vertical DMOS Specific On-resistance", IEDM Tech. Dig., 736, 1985
9. B. J. Baliga, "Modern Power Device", John Wiley Sons, 350, 1987
10. H. Milehner, et al, "A Novel 8 kV Light-Trigger Thyristor with Over Voltage Self Protection", Proc. ISPSD, 289, 1990
For the self-extinguish type power transistors, there have been proposed a buried gate type GTO thyristor and a buried gate type SI thyristor, in which gate regions are formed in a surface of a semiconductor substrate and then an epitaxial layer is formed on the surface of the semiconductor substrate such that the gate regions are buried. In this case, a growth of the epitaxial layer has a substrate dependency. That is, crystal growth and impurity density distribution of the epitaxial layer formed on the gate region differ from those of the epitaxial layer formed on the surface of the semiconductor substrate. Due to such a substrate dependency of the epitaxial layer, it is difficult of obtain a semiconductor device having good properties. Further, the epitaxial growth is a process which requires a relatively long time period, so that the efficency of manufacturing such a buried gate type semiconductor device is low. Moreover, the conductivity type of a semiconductor region in the vicinity of the gate region is likely to be inverted. In order to mitigate the above mentioned drawbacks, there has been proposed a surface gate type structure, in which gate regions are formed in a surface of a semiconductor substrate. However, in such a surface gate type semiconductor device, a large gate reverse voltage could not be attained and thus a large current could not be interrupted.
In the known GTO thyristors, it is impossible to increase an impurity concentration of the gate region, and therefore a carrier drawing speed is low so that a turn-off loss is large and an operating frequency is low.
In order to overcome the above mentioned problems of the buried gate type semiconductor devices, there has been proposed a serration gate structure, in which relatively deep recesses are formed in a surface of a semiconductor substrate and gate regions are formed at bottoms of these recesses. However, it is rather difficult to form the deep recesses even by using a dry etching, and thus it is impossible to obtain a sufficiently high breakdown voltage. Moreover, a precision working for forming the deep recesses is liable to be complicated.
The inventor of the instant application has proposed, in U. S. patent application Ser. No. 08/407,023 as well as in a corresponding European Patent Application No. 94 921826.7 contact type or joined type semiconductor devices. In one type of these semiconductor devices, recesses or depressions are formed in a surface of a first semiconductor substrate, impurities are introduced into the semiconductor substrate from bottoms of the depressions to form gate regions each having a high impurity concentration, gate electrodes are formed on respective gate regions and a second semiconductor substrate is joined to the surface of the first semiconductor substrate. In another type, gate regions each having a high impurity concentration are formed in a surface of a first semiconductor substrate, gate electrodes are formed on respective gate regions, and a second semiconductor substrate having depressions formed in a surface thereof is joined to the surface of the first semiconductor substrate such that the gate electrodes are accommodated in respective depressions formed in the surface of the second semiconductor substrate. In these joined type semiconductor devices, the above mentioned various drawbacks caused by the epitaxial growth can be removed. Therefore, in a joined type GTO thyristor, the impurity concentration of the gate regions can be easily made high, and thus carriers can be drawn at a high speed so that the operating frequency can be raised. In the joined type SI thyristor, the gate regions having a high impurity concentration can be buried uniformly, a large area can be easily realized.
In the above mentioned joined type semiconductor devices, the manufacturing process can be effectively simplified, but a distance between a channel region radiating heat and an electrode having a function for dissipating the heat is long, so that a cooling could not be performed efficiently. This might result in a malfunction of the semiconductor device. Moreover, the gate structures are surrounded in the depressions formed in the surfaces of the first and/or second semiconductor substrates, and thus there exist vacant spaces above the gate structures. This results in a decrease in a mechanical strength and a decrease in cooling efficiency.